1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC), and more particularly, to a clock control apparatus of a semiconductor IC.
2. Related Art
In general, a semiconductor IC includes a clock generating circuit, such as a Delay Locked Loop (DLL) circuit and a Phase Locked Loop (PLL) circuit, to generate an internal clock signal having a phase faster than an external clock signal by a predetermined time. Accordingly, the internal clock signal generated in this way is used to synchronize timing for buffering data during data input/output operations.
Since a frequency of the internal clock signal determines an operational speed of a semiconductor IC, a clock generating circuit is provided to generate an internal clock signal having a higher frequency in order to improve the operational speed. Accordingly, semiconductor ICs include a method for oscillating a clock signal having a relatively high frequency by using the PLL circuit. In addition, the semiconductor ICs include a method of dividing a clock signal into a plurality of individual frequencies by using a mufti-phase DLL circuit.
Currently, semiconductor ICs use a PLL circuit for oscillating a PLL clock signal by using a reference clock signal input through a clock signal input buffer, and then transmitting the buffered clock signal input to a data input/output circuit along a relatively long conductive transmission line to generate an internal clock signal by using a DLL circuit. Here, the DLL circuit is implemented as a multi-phase DLL circuit, and the internal clock signal is implemented as a set of clock signals each having multiple phases. However, using both a PLL circuit and a DLL circuit in one semiconductor IC degrades internal area efficiency of a semiconductor IC, thereby preventing high integration of the semiconductor IC. In addition, since both the PLL and DLL circuits are provided together, consumption power greatly increases. Thus, the semiconductor IC fails to maintain a low power consumption, thereby reducing power efficiency of the semiconductor IC.